1. Field of the Invention
The present invention is directed to a digital delay-locked loop for synchronizing an operation of a semiconductor integrated circuit to an external clock signal, and in particular to a digital delay-locked loop capable of performing a synchronization of an internal clock signal to an external clock signal within a short time by compensating for a delay time of a clock buffer, and repeatedly sampling the external clock signal for low power consumption.
2. Description of the Background Art
A phase-locked loop PLL and a delay-locked loop DLL are utilized for compensating for the delay time generated when an internal clock signal used by an internal circuit is to be operated at high speed in synchronization with an external clock signal which drives a high load capacitance.
As illustrated in FIG. 1, a conventional digital delay-locked loop includes: an input buffer BUF1 buffering an externally inputted clock signal CLKX and outputting the buffered signal CLKR; an internal clock buffer BUF2 buffering a delayed clock signal CLKD and outputting a buffered signal CLKQ for driving an external load capacitance; a reference delay block 10 having a fixed delay element and determining a phase relation of the outputted delayed signal CLKQ with the externally inputted clock signal CLKX and outputting a signal CLKI; a variable delay block 20 consisting of a delay chain 20-1 having unit delay time TD and a register chain 20-2, for controlling the delay time of the delayed clock signal CLKD; and a phase detector 30 comparing the phase of a feedback clock signal CLKI delayed by the reference delay block 10 with that of the buffered input clock signal CLKR.
The phase detector 30 includes: D-type flip-flops DFF11-DFF13 being synchronized by the input clock signal CLKR outputted from the input buffer BUF1; an output logic unit OUTL logically operating the Q output signals of the flip-lops DFF11-DFF13, the inverted Q output signals of the D-flip-flops DFF12, DFF13 and an initializing signal INI, and outputting a synchronous signal LOCK, a shift right signal SHR and a shift left signal SHL; an input logic unit INL logically combining a comparison signal QBEG outputted from the register chain 20-2 of the variable delay block 20, the Q output signal of the flip-flop DFF12 and the inverted Qb output signals of the flip-flops DFF11-DFF13, and driving the D data input of the flip-flops DFF11, DFF12; and a clock divider 30-1 dividing the input clock signal CLKR by two and outputting a sampling clock signal CLKS.
The output logic unit OUTL includes: inverters INV11, INV12 sequentially inverting the Q output signal of the first flip-flop DFF11 and outputting the synchronous signal LOCK; a NAND gate ND11 NANDing the initialization signal INI and the Q output signals of the second and third flip-flops DFF12, DFF13; an inverter INV13 inverting an output signal of the NAND gate ND11 and outputting the shift left signal SHL; an OR gate OR11 ORing the inverted Qb output signal of the second and third flip-flops DFF12, DFF13; a NAND gate ND12 NANDing an output signal of the OR gate OR11 and the initialization signal INI; and an inverter INV14 inverting an output signal of the NAND gate ND12 and outputting the shift right signal SHR.
The input logic unit INL includes: an inverter INV15 inverting the comparison signal QBEG outputted from the register chain 20-2 at the variable delay block 20; an AND gate AND11 which ANDs the inverted Qb output signals of the second and third flip-flops DFF12, DFF13; a NOR gate NOR11 NORing an output signal of the AND gate AND11 and an output signal of the inverter INV15 and driving the D input of the second flip-flop DFF12; a NAND gate ND13 NANDing the Q output signal Df the second flip-flop DFF12 and the inverted Qb output signal of the third flip-flop DFF13; an AND gate AND12 ANDing an output signal of the NAND gate NAND13 and the inverted Qb output signal of the first flip-flop DFF11; and a NOR gate NOR12 where an output signal of the AND gate AND12 and an output of the inverter INV15 and driving the D input of the first flip-flop DFF11.
As illustrated in FIG. 2, in the variable delay block 20, as outputs of the register chain 20-2 are sequentially inputted to the delay chain 20-1 and control it, the input clock signal CLKR is inputted to the delay chain 20-1 and the internal clock signal CLKD is outputted therefrom, and the shift left signal SHL, the shift right signal SHR and the sampling clock signal CLKS are inputted to the register chain 20-2, and the comparison signal QBEG is finally outputted therefrom.
As shown in FIG. 3, the Ith delay block 20-1(I) of the delay chain 20-1 includes: an inverter INV31 inverting an output signal X(I-1) of a next preceding delay block 20-1(I-1); a transmission gate TG31 controlled by an output signal Q(I-1) of a next preceding register block 20-2(I-1) and the inverted output signal Qb(I-1) thereof, and selecting and outputting an output of the inverter INV31; an NMOS transistor NM31 the drain of which is connected to an output terminal of the transmit gate TG31, the source of which connected to a ground voltage VSS, and the gate of which receives the inverted output signal Qb(I-1) of the preceding register block 20-2(I-1); a transmission gate TG32 controlled by an output signal Q(I) of the Ith register block 20-2(I) and the inverted output signal Qb(I) thereof, and selecting and outputting an output signal Y(I+1) of a next succeeding delay block 20-1(I+1); an inverter INV32 inverting the output Y(I+1) of the delay block 20-1(I+1) selected and outputted by the transmission gate TG32; and a transmission gate TG33 connected between an input terminal of the inverter INV32 and an output terminal of the inverter INV31 and controlled by the output signal Q(I) of the register block 20-2(I) and the inverted output signal Qb(I) thereof, for playing a switching role.
As illustrated in FIG. 4, the Ith register block 20-2(I) of the register chain 20-2 includes: a NAND gate ND41 NANDing the shift right signal SHR and the output signal Q(I-1) of the next preceding register block 20-2(I-1); a NAND gate ND42 NANDing the shift left signal SHL and an output signal Q(I+1) of a next succeeding register block 20-2(I+1); an NAND gate ND43 NANDing the output signals of the NAND gates ND41, ND42; and an edge trigger D-type flip-flop DFF41 synchronized by the sampling clock signal CLKS, and receiving an output signal of the NAND gate ND43 at its D input.
The operation of the above-described conventional digital delay-locked loop will now be described with reference to FIG. 5.
First, register blocks 20-2(l).about.20-2(N) are all reset at the initial stage. At this time, the input clock signal CLKR is passed through the variable delay time block 20 and a feedback loop, namely the reference delay block 10, produce an initial internal clock signal CLKI(0). The phase detector 30 outputs the shift right signal SHR regardless of the phase relationship between the input clock signal CLKR and the initial internal clock signal CLKI(0). The value of the Ith register block 20-2(I) in the variable delay block 20 is determined in accordance with the phase comparison signals SHR/SHL and the output signals Q(I-1), Q(I+1) of the I-1th and I+1th register blocks 20-2(I-1), 20-2(I+1) at a rising edge of the sampling clock signal CLKS, and the value is incremented by one step according to the sampling clock signal CLKS from the initial stage with phase synchronization.
At this time, in order to guarantee a margin for inputting the feedback clock signal CLKI delayed by the sampling clock signal CLKS to the phase detector 30 before being re-delayed by the next sampling clock signal CLKS, the sampling clock signal CLKS become an input clock signal CLKR divided by two in the clock divider 30-1.
As shown in FIG. 5, when a high section of the feedback clock signal CLKI delayed to a rising edge of the input clock signal CLKR is detected, it is located at a phase detect region PD region. In the case that a low section of a feedback clock signal CLKI(I) delayed due to a sampling clock signal CLKS to a rising edge of the input clock signal CLKR by repeating a delay operation as long as the unit delay time TD for every rising edge of the sampling clock signal CLKS, is detected, the phase is synchronized. Here, the phase detector 30 outputs the shift left signal SHL, the unit delay time TD is advanced by one step due to a sampling signal CLKS, and thus the phase of the feedback clock signal CLKI(I) is identical to that of a I-1th feedback clock signal CLKI(I-1). The phase detector 30 outputs the shift right signal SHR by the phase relation between the input clock signal CLKR and the I-1th feedback clock signal CLKI(I-1), an initial feedback clock signal CLKI(0) is delayed by one step due to a sampling clock signal CLKS, and thus the phase of the feedback clock signal CLKI(0) is identical to that of the I-th feedback clock signal CLKI(I). That is, the feedback clock signal CLKI interrupts an operation of the delay-locked loop for as long as the unit delay time TD to the input clock signal CLKR, and the output clock signal CLKQ and the feedback clock signal CLKI become low. However, the previous values are saved in the phase detector 30 and the register block chain 20-2 of the variable delay time block 20. When the external clock signal CLKX is inputted, the unit delay time TD before the input clock signal CLKR is intercepted is set and a phase synchronized operation is performed.
The time to the initial phase synchronization in accordance with the conventional art is as follows.
A minimum loop delay time is represented by the following equation. EQU Tml=td+tref (1)
At this time, the number of stages N of the unit delay time TD demanded until the phase synchronization is obtained by the following equation. EQU N=(Tclk-Tml)/TD (2)
The time Tlock to the phase synchronization is represented by the following equation. EQU Tlock=CLKS*N (3)
That is, when the equation `Tclk-Tml&gt;TD` is satisfied, the time to the phase synchronization is obtained by the following equation. EQU Tlock=2Tclk(Tclk-Tml)/TD (4)
The synchronization time is in proportion to the square of Tclk. When the minimum loop delay time Tml is determined, the synchronization setting time may be lengthened at low frequency, namely, when the clock period is long.
Especially, in case the relation `Tclk/2&gt;Tml` is satisfied, a longer unit delay time TD is demanded until the feedback clock signal CLKI is located within the initial phase detect region.
However, such an operation obstructs rapid synchronization setting, and consequently, becomes an disadvantage in an integrated circuit demanding a rapid synchronization setting.
In addition, the conventional phase-locked loop PLL and delay-locked loop DLL utilize analog circuits such as a charge pump and a voltage controlled oscillator VCO in order to perform a phase synchronization operation of an input clock signal and an internal clock signal, and require multiple cycles for performing the phase synchronization. Therefore, a synchronous dynamic random access memory SDRAM which must operate a synchronized to an input clock signal and which has an active mode (read/write operation) and a refresh mode is not capable of achieving a rapid phase synchronization in converting its operation from the refresh mode while cutting off the input clock signal to the active mode for low-power operation. That is, the SDRAM cannot cut off the input clock signal for rapid operation conversion, and thus there is a disadvantage that the SDRAM cannot perform a low-power operation.
Further, in the worst case, the phase of a rising edge of the first feedback clock signal is different from that of a target rising edge by one period. Here, in order to lock to a target edge, various delay factors are demanded, and thus it takes a longer time to lock. Especially, in case of a low-frequency clock signal whose period is long, it takes a much longer time to lock.